Different Intel Processors


Details of different processors of Intel
Intel 4004
first single-chip microprocessor
  • Introduced November 15, 1971
  • Clock rate 740 KHz
  • 0.07 MIPS
  • Bus Width 4 bits (multiplexed address/data due to limited pins)
  • Number of Transistors 2,300 at 10 µm
  • Addressable Memory 640 bytes
  • Program Memory 4 KB (4 KB)
  • One of the earliest Commercial  Microprocessors (cf. Four Phase Systems AL1, F14 CADC)
  • Originally designed to be used in Busicom calculator
MCS-4 Family:
  • 4004 – CPU
  • 4001 – ROM & 4-Bit Port
  • 4002 – RAM & 4-Bit Port
  • 4003 – 10-Bit Shift Register
  • 4008 – Memory+I/O Interface
  • 4009 – Memory+I/O Interface

Intel 4040

MCS-40 Family:

  • 4040 – CPU
  • 4101 – 1024-bit (256 × 4) Static RAM with separate I/O
  • 4201 – 4 MHz Clock Generator
  • 4207 – General Purpose Byte I/O Port
  • 4209 – General Purpose Byte I/O Port
  • 4211 – General Purpose Byte I/O Port
  • 4265 – Programmable General Purpose I/O Device
  • 4269 – Programmable Keyboard Display Device
  • 4289 – Standard Memory Interface for MCS-4/40
  • 4308 – 8192-bit (1024 × 8) ROM w/ 4-bit I/O Ports
  • 4316 – 16384-bit (2048 × 8) Static ROM
  • 4702 – 2048-bit (256 × 8) EPROM
  • 4801 – 5.185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A 

The 8-bit Processors

8008

  • Introduced April 1, 1972
  • Clock rate 500 kHz (8008–1: 800 kHz)
  • 0.05 MIPS
  • Bus Width 8 bits (multiplexed address/data due to limited pins)
  • Enhancement load PMOS logic
  • Number of Transistors 3,500 at 10 µm
  • Addressable memory 16 KB
  • Typical in early 8-bit microcomputers, dumb terminals, general calculators, bottling machines
  • Developed in tandem with 4004
  • Originally intended for use in the Datapoint 2200 microcomputer
  • Key volume deployment in Texas Instruments 742 microcomputer in >3,000 Ford dealerships

8080

  • Introduced April 1, 1974
  • Clock rate 2 MHz (very rare 8080B: 3 MHz)
  • 0.29 MIPS
  • Bus Width 8 bits data, 16 bits address
  • Enhancement load NMOS logic
  • Number of Transistors 6,000, 6μm
  • Assembly language downwards compatible with 8008.
  • Addressable memory 64 KB
  • Up to 10X the performance of the 8008
  • Used in the Altair 8800, Traffic light controller, cruise missile
  • Required six support chips versus 20 for the 8008

8085

  • Introduced March 1976
  • Clock rate 3 MHz 
  • 0.37 MIPS
  • Bus Width 8 bits data, 16 bits address
  • Depletion load NMOS logic
  • Number of Transistors 6,500 at 3 µm
  • Binary compatible downwards with the 8080.
  • Used in Toledo scales. Also was used as a computer peripheral controller – modems, hard disks, printers, etc.
  • CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable.
  • High level of integration, operating for the first time on a single 5-volt power supply, from 12 volts previously. Also featured serial I/O, 3 maskable interrupts, 1 non-maskable interrupt, 1 externally expandable interrupt w/[8259], status, DMA.
  • MCS-85 family contains processors and peripherals
Microcontrollers They are IC's with CPU, RAM, ROM (or PROM or EPROM), I/O Ports, Timers & Interrupts
Intel 8048 Single accumulator /Harvard architecture
MCS-48 family 8020 – Single-Component 8-Bit Microcontroller 8021 – Single-Component 8-Bit Microcontroller 8022 – Single-Component 8-Bit Microcontroller With On-Chip A/D Converter 8035 – Single-Component 8-Bit Microcontroller 8039 – Single-Component 8-Bit Microcontroller 8040 – Single-Component 8-Bit Microcontroller*8041 – Universal Peripheral Interface 8-Bit Slave Microcontroller 8641 – Universal Peripheral Interface 8-Bit Slave Microcontroller 8741 – Universal Peripheral Interface 8-Bit Slave Microcontroller 8042 – Universal Peripheral Interface 8-Bit Slave Microcontroller 8742 – Universal Peripheral Interface 8-Bit Slave Microcontroller 8243 – Input/Output Expander 8048 – Single-Component 8-Bit Microcontroller 8048 – Single-Component 8-Bit Microcontroller 8748 – Single-Component 8-Bit Microcontroller 8048 – Single-Component 8-Bit Microcontroller 8049 – Single-Component 8-Bit Microcontroller 8749 – Single-Component 8-Bit Microcontroller 8050 – Single-Component 8-Bit Microcontroller
Intel 80515 Single accumulator /computing accumulator
MCS-51 Family: 8031 – 8-Bit Control-Oriented Microcontroller 8032 – 8-Bit Control-Oriented Microcontroller 8044 – High Performance 8-Bit Microcontroller 8344 – High Performance 8-Bit Microcontroller 8744 – High Performance 8-Bit Microcontroller 8051 – 8-Bit Control-Oriented Microcontroller 8052 – 8-Bit Control-Oriented Microcontroller 8054 – 8-Bit Control-Oriented Microcontroller 8058 – 8-Bit Control-Oriented Microcontroller 8351 – 8-Bit Control-Oriented Microcontroller 8352 – 8-Bit Control-Oriented Microcontroller 8354 – 8-Bit Control-Oriented Microcontroller 8358 – 8-Bit Control-Oriented Microcontroller 8751 – 8-Bit Control-Oriented Microcontroller 8752 – 8-Bit Control-Oriented Microcontroller 8754 – 8-Bit Control-Oriented Microcontroller 8758 – 8-Bit Control-Oriented Microcontroller
Intel 80151 Single accumulator /computing accumulator /Harvard architecture
MCS-151 Family: 80151 – High Performance 8-Bit Control-Oriented Microcontroller 83151 – High Performance 8-Bit Control-Oriented Microcontroller 87151 – High Performance 8-Bit Control-Oriented Microcontroller 80152 – High Performance 8-Bit Control-Oriented Microcontroller 83152 – High Performance 8-Bit Control-Oriented Microcontroller

Intel 80251

Single accumulator Harvard architecture

MCS-251 Family:
  • 80251 – 8/16/32-Bit Microcontroller
  • 80252 – 8/16/32-Bit Microcontroller
  • 80452 – 8/16/32-Bit Microcontroller
  • 83251 – 8/16/32-Bit Microcontroller
  • 87251 – 8/16/32-Bit Microcontroller
  • 87253 – 8/16/32-Bit Microcontroller

MCS-96 Family

  • 8094 – 16-Bit Microcontroller (48-Pin ROMLess Without A/D)
  • 8095 – 16-Bit Microcontroller (48-Pin ROMLess With A/D)
  • 8096 – 16-Bit Microcontroller (68-Pin ROMLess Without A/D)
  • 8097 – 16-Bit Microcontroller (68-Pin ROMLess With A/D)
  • 8394 – 16-Bit Microcontroller (48-Pin With ROM Without A/D)
  • 8395 – 16-Bit Microcontroller (48-Pin With ROM With A/D)
  • 8396 – 16-Bit Microcontroller (68-Pin With ROM Without A/D)
  • 8397 – 16-Bit Microcontroller (68-Pin With ROM With A/D)
  • 8794 – 16-Bit Microcontroller (48-Pin With EROM Without A/D)
  • 8795 – 16-Bit Microcontroller (48-Pin With EROM With A/D)
  • 8796 – 16-Bit Microcontroller (68-Pin With EROM Without A/D)
  • 8797 – 16-Bit Microcontroller (68-Pin With EROM With A/D)
  • 8098 – 16-Bit Microcontroller
  • 8398 – 16-Bit Microcontroller
  • 8798 – 16-Bit Microcontroller
  • 80196 – 16-Bit Microcontroller
  • 83196 – 16-Bit Microcontroller
  • 87196 – 16-Bit Microcontroller
  • 80296 – 16-Bit Microcontroller

The bit-slice processor

3000 family
Introduced in the third quarter of 1974, these components used bipolar Schottky transistors. Each component implemented two bits of a processor function; packages could be interconnected to build a processor with any desired word length. Members of the family:
  • 3001 – Microcontrol Unit
  • 3002 – 2-bit Arithmetic Logic Unit slice
  • 3003 – Look-ahead Carry Generator
  • 3205 – High-performance 1 Of 8 Binary Decoder
  • 3207 – Quad Bipolar-to-MOS Level Shifter and Driver
  • 3208 – Hex Sense Amp and Latch for MOS Memories
  • 3210 – TTL-to-MOS Level Shifter and High Voltage Clock Driver
  • 3211 – ECL-to-MOS Level Shifter and High Voltage Clock Driver
  • 3212 – Multimode Latch Buffer
  • 3214 – Interrupt Control Unit
  • 3216 – Parallel,Inverting Bi-Directional Bus Driver
  • 3222 – Refresh Controller for 4K NMOS DRAMs
  • 3226 – Parallel, Inverting Bi-Directional Bus Driver
  • 3232 – Address Multiplexer and Refresh Counter for 4K DRAMs
  • 3242 – Address Multiplexer and Refresh Counter for 16K DRAMs
  • 3245 – Quad Bipolar TTL-to-MOS Level Shifter and Driver for 4K
  • 3246 – Quad Bipolar ECL-to-MOS Level Shifter and Driver for 4K
  • 3404 – High-performance 6-bit Latch
  • 3408 – Hex Sense Amp and Latch for MOS Memories
Bus Width 2*n bits data/address (depending on number n of slices used)

The 16-bit processors: MCS -86 family

8086

  • Introduced June 8, 1978
  • Clock rates:
    • 5 MHz with 0.33 MIPS
    • 8 MHz with 0.66 MIPS
    • 10 MHz with 0.75 MIPS
  • The memory is divided into odd and even banks; it accesses both banks concurrently to read 16 bits of data in one clock cycle
  • Bus Width 16 bits data, 20 bits address
  • Number of Transistors 29,000 at 3 µm
  • Addressable memory 1 megabyte
  • Up to 10X the performance of 8080
  • Used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line).
  • Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.[citation needed]

8088

  • Introduced June 1, 1979
  • Clock rates:
    • 5 MHz with 0.33 MIPS
    • 8 MHz with 0.66 MIPS 
  • Internal architecture 16 bits
  • External bus Width 8 bits data, 20 bits address
  • Number of Transistors 29,000 at 3 µm
  • Addressable memory 1 megabyte
  • Identical to 8086 except for its 8-bit external bus (hence an 8 instead of a 6 at the end)
  • Used in IBM PCs and PC clones

80186

  • Introduced 1982
  • Clock rates
    • 6 MHz with > 1 MIPS
  • Number of Transistors 29,000 at 2 µm
  • Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor (these were at fixed addresses which differed from the IBM PC, making it impossible to build a 100% PC-compatible computer around the 80186).
  • Added a few opcodes and exceptions to the 8086 design; otherwise identical instruction set to 8086 and 8088.
  • Used mostly in embedded applications – controllers, point-of-sale systems, terminals, and the like
  • Used in several non-PC-Compatible MS-DOS computers including RM Nimbus, Tandy 2000, and CP/M 86 Televideo PM16 server
  • Later renamed the iAPX 186

80188

  • A version of the 80186 with an 8-bit external data bus
  • Later renamed the iAPX 188

80286

  • Introduced February 1, 1982
  • Clock rates:
    • 6 MHz with 0.9 MIPS
    • 8 MHz, 10 MHz with 1.5 MIPS
    • 12.5 MHz with 2.66 MIPS
    • 16 MHz, 20 MHz and 25 MHz available.
  • Bus Width: 16 bits data, 24 bits address.
  • Included memory protection hardware to support multitasking operating systems with per-process address space
  • Number of Transistors 134,000 at 1.5 µm
  • Addressable memory 16 MB
  • Added protected-mode features to 8086 with essentially the same instruction set
  • 3–6X the performance of the 8086
  • Widely used in IBM-PC AT and AT clones contemporary to it

32-bit processors:non MCS-x86 microprocessors

iAPX 432

  • Introduced January 1, 1981 as Intel's first 32-bit microprocessor
  • Multi-chip CPU; Intel's first 32-bit microprocessor
  • Object/capability architecture
  • Microcoded operating system primitives
  • One terabyte virtual address space
  • Hardware support for fault tolerance
  • Two-chip General Data Processor (GDP), consists of 43201 and 43202
  • 43203 Interface Processor (IP) interfaces to I/O subsystem
  • 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
  • 43205 Memory Control Unit (MCU)
  • Architecture and execution unit internal data base paths 32 bit
  • Clock rates:
    • 5 MHz
    • 7 MHz
    • 8 MHz

i960 aka 80960

  • Introduced April 5, 1988
  • RISC-like 32-bit architecture
  • Predominantly used in embedded systems
  • Evolved from the capability processor developed for the BiiN joint venture with Siemens
  • Many variants identified by two-letter suffixes.

i860 aka 80860

  • Introduced February 27, 1989
  • RISC 32/64-bit architecture, with floating point pipeline characteristics very visible to programmer
  • Used in the Intel iPSC/860 Hypercube parallel supercomputer
  • Mid-life kicker in the i870 processor (primarily a speed bump, some refinement/extension of instruction set)
  • Used in the Intel Delta massively parallel supercomputer prototype, emplaced at California Institute of Technology
  • Used in the Intel Paragon massively parallel supercomputer, emplaced at Sandia National Laboratory

XScale

  • Introduced August 23, 2000
  • 32-bit RISC microprocessor based on the ARM architecture
  • Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.

32-bit processors :the 80386 range

80386DX

  • Introduced October 17, 1985
  • Clock rates:
    • 16 MHz with 5 MIPS
    • 20 MHz with 6 to 7 MIPS, introduced February 16, 1987
    • 25 MHz with 7.5 MIPS, introduced April 4, 1988
    • 33 MHz with 9.9 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced April 10, 1989
  • Bus Width 32 bits data, 32 bits address
  • Number of Transistors 275,000 at 1 µm
  • Addressable memory 4 GB
  • Virtual memory 64 TB
  • First x86 chip to handle 32-bit data sets
  • Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required at the time by Xenix and Unix. This memory capability spurred the development and availability of OS/2 and is a fundamental requirement for modern operating systems like Linux, Windows, and Mac OS.
  • Used in desktop computing

80386SX

  • Introduced June 16, 1988
  • Clock rates:
    • 16 MHz with 2.5 MIPS
    • 20 MHz with 3.1 MIPS, introduced January 25, 1989
    • 25 MHz with 3.9 MIPS, introduced January 25, 1989
    • 33 MHz with 5.1 MIPS, introduced October 26, 1992
  • Internal architecture 32 bits
  • External data bus width 16 bits
  • External address bus width 24 bits
  • Number of Transistors 275,000 at 1 µm
  • Addressable memory 16 MB
  • Virtual memory 32 GB
  • Narrower buses enable low-cost 32-bit processing
  • Used in entry-level desktop and portable computing
  • No Math Co-Processor
  • No commercial Software used for protected mode or virtual storage for many years

80376

80386SL

  • Introduced January 16, 1989; discontinued June 15, 2001
  • Variant of 386SX intended for embedded systems
  • No "real mode", starts up directly in "protected mode"
  • Replaced by much more successful 80386EX from 1994
  • Introduced October 15, 1990
  • Clock rates:
    • 20 MHz with 4.21 MIPS
    • 25 MHz with 5.3 MIPS, introduced September 30, 1991
  • Internal architecture 32 bits
  • External bus width 16 bits
  • Number of Transistors 855,000 at 1 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • First chip specifically made for portable computers because of low power consumption of chip
  • Highly integrated, includes cache, bus, and memory controllers

80386EX

  • Introduced August 1994
  • Variant of 80386SX intended for embedded systems
  • Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
  • On-chip peripherals:
    • Clock and power management
    • Timers/counters
    • Watchdog timer
    • Serial I/O units (sync and async) and parallel I/O
    • DMA
    • RAM refresh
    • JTAG test logic
  • Significantly more successful than the 80376
  • Used aboard several orbiting satellites and microsatellites
  • Used in NASA's FlightLinux project

32-bit processors :the 80486 range

80486DX

  • Introduced April 10, 1989
  • Clock rates:
    • 25 MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
    • 33 MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128 KB L2), introduced May 7, 1990
    • 50 MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256 KB L2), introduced June 24, 1991
  • Bus Width 32 bits
  • Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • Level 1 cache of 8 KB on chip
  • Math coprocessor on chip
  • 50X performance of the 8088
  • Used in Desktop computing and servers
  • Family 4 model 3

80486SX

  • Introduced April 22, 1991
  • Clock rates:
    • 16 MHz with 13 MIPS
    • 20 MHz with 16.5 MIPS, introduced September 16, 1991
    • 25 MHz with 20 MIPS (12 SPECint92), introduced September 16, 1991
    • 33 MHz with 27 MIPS (15.86 SPECint92), introduced September 21, 1992
  • Bus Width 32 bits
  • Number of Transistors 1.185 million at 1 µm and 900,000 at 0.8 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • Identical in design to 486DX but without math coprocessor. The first version was an 80486DX with disabled math coprocessor in the chip and different pin configuration. If the user needed math coprocessor capabilities, he must add 487SX which was actually an 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPU's with only 1 effectively turned on
  • Used in low-cost entry to 486 CPU desktop computing, as well as extensively used in low cost mobile computing.
  • Upgradable with the Intel OverDrive processor
  • Family 4 model 2

80486DX2

Introduced March 3, 1992

Runs at twice the speed of the external bus (FSB). Fits on Socket 3
  • Clock rates:
    • 40 MHz
    • 50 MHz
    • 66 MHz

80486SL

  • Introduced November 9, 1992
  • Clock rates:
    • 20 MHz with 15.4MIPS
    • 25 MHz with 19 MIPS
    • 33 MHz with 25 MIPS
  • Bus Width 32 bits
  • Number of Transistors 1.4 million at 0.8 µm
  • Addressable memory 4 GB
  • Virtual memory 1 TB
  • Used in notebook computers
  • Family 4 model 3

80486DX4

  • Introduced March 7, 1994
  • Clock rates:
    • 75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KB L2)
    • 100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KB L2)
  • Number of Transistors 1.6 million at 0.6 µm
  • Bus width 32 bits
  • Addressable memory 4 GB
  • Virtual memory 64 TB
  • Pin count 168 PGA Package, 208 sq ftP Package
  • Used in high performance entry-level desktops and value notebooks
  • Family 4 model 8

32-bit processors: P5 microarchitecture

Original Pentium

  • Bus width 64 bits
  • System bus clock rate 60 or 66 MHz
  • Address bus 32 bits
  • Addressable Memory 4 GB
  • Virtual Memory 64 TB
  • Superscalar architecture
  • Runs on 5 volts
  • Used in desktops
  • 8 KB of instruction cache
  • 8 KB of data cache
  • P5 – 0.8 µm process technology
    • Introduced March 22, 1993
    • Number of transistors 3.1 million
    • Socket 4 273 pin PGA processor package
    • Package dimensions 2.16" × 2.16"
    • Family 5 model 1
    • Variants
      • 60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KB L2)
      • 66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KB L2)
  • P54 – 0.6 µm process technology
    • Socket 5 296/320 pin PGA package
    • Number of transistors 3.2 million
    • Variants
      • 75 MHz with 126.5 MIPS (2.31 SPECint95, 2.02 SPECfp95 on Gateway P5 256K L2)
        • Introduced October 10, 1994
      • 90, 100 MHz with 149.8 and 166.3 MIPS respectively (2.74 SPECint95, 2.39 SPECfp95 on Gateway P5 256K L2 and 3.30 SPECint95, 2.59 SPECfp95 on Xpress 1ML2 respectively)
        • Introduced March 7, 1994
  • P54CQS – 0.35 µm process technology
    • Socket 5 296/320 pin PGA package
    • Number of transistors 3.2 million
    • Variants
      • 120 MHz with 203 MIPS (3.72 SPECint95, 2.81 SPECfp95 on Xpress 1MB L2)
        • Introduced March 27, 1995
  • P54CS – 0.35 µm process technology
    • Number of transistors 3.3 million
    • 90 mm² die size
    • Family 5 model 2
    • Variants
    • Socket 5 296/320 pin PGA package
      • 133 MHz with 218.9 MIPS (4.14 SPECint95, 3.12 SPECfp95 on Xpress 1MB L2)
        • Introduced June 12, 1995
      • 150, 166 MHz with 230 and 247 MIPS respectively
        • Introduced January 4, 1996
    • Socket 7 296/321 pin PGA package
      • 200 MHz with 270 MIPS (5.47 SPECint95, 3.68 SPECfp95)
        • Introduced June 10, 1996

Pentium with MMX Technology

  • P55C – 0.35 µm process technology
    • Introduced January 8, 1997
    • Intel MMX (instruction set) support
    • Socket 7 296/321 pin PGA (pin grid array) package
    • 16 KB L1 instruction cache
    • 16 KB L1 data cache
    • Number of transistors 4.5 million
    • System bus clock rate 66 MHz
    • Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
    • Variants
      • 166, 200 MHz Introduced January 8, 1997
      • 233 MHz Introduced June 2, 1997
      • 133 MHz (Mobile)
      • 166, 266 MHz (Mobile) Introduced January 12, 1998
      • 200, 233 MHz (Mobile) Introduced September 8, 1997
      • 300 MHz (Mobile) Introduced January 7, 1999

32-bit processors: p6/Pentium M microarchitecture


Pentium Pro

  • Introduced November 1, 1995
  • Precursor to Pentium II and III
  • Primarily used in server systems
  • Socket 8 processor package (387 pins) (Dual SPGA)
  • Number of transistors 5.5 million
  • Family 6 model 1
  • 0.6 µm process technology
    • 16 KB L1 cache
    • 256 KB integrated L2 cache
    • 60 MHz system bus clock rate
    • Variants
      • 150 MHz
  • 0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache
    • Number of transistors 5.5 million
    • 512 KB or 256 KB integrated L2 cache
    • 60 or 66 MHz system bus clock rate
    • Variants
      • 166 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
      • 180 MHz (60 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
      • 200 MHz (66 MHz bus clock rate, 256 KB 0.6 µm cache) Introduced November 1, 1995
      • 200 MHz (66 MHz bus clock rate, 512 KB 0.35 µm cache) Introduced November 1, 1995
      • 200 MHz (66 MHz bus clock rate, 1 MB 0.35 µm cache) Introduced August 18, 1997

Pentium II

  • Introduced May 7, 1997
  • Pentium Pro with MMX and improved 16-bit performance
  • 242-pin Slot 1 (SEC) processor package
  • Voltage identification pins
  • Number of transistors 7.5 million
  • 32 KB L1 cache
  • 512 KB ½ bandwidth external L2 cache
  • The only Pentium II that did not have the L2 cache at ½ bandwidth of the core was the Pentium II 450 PE.
  • Klamath – 0.35 µm process technology (233, 266, 300 MHz)
    • 66 MHz system bus clock rate
    • Family 6 model 3
    • Variants
      • 233, 266, 300 MHz Introduced May 7, 1997
  • Deschutes – 0.25 µm process technology (333, 350, 400, 450 MHz)
    • Introduced January 26, 1998
    • 66 MHz system bus clock rate (333 MHz variant), 100 MHz system bus clock rate for all models after
    • Family 6 model 5
    • Variants
      • 333 MHz Introduced January 26, 1998
      • 350, 400 MHz Introduced April 15, 1998
      • 450 MHz Introduced August 24, 1998
      • 233, 266 MHz (Mobile) Introduced April 2, 1998
      • 333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998; 
      • 300 MHz (Mobile) Introduced September 9, 1998
      • 333 MHz (Mobile)

Celeron (Pentium II-based)

  • Covington – 0.25 µm process technology
    • Introduced April 15, 1998
    • 242-pin Slot 1 SEPP (Single Edge Processor Package)
    • Number of transistors 7.5 million
    • 66 MHz system bus clock rate
    • Slot 1
    • 32 KB L1 cache
    • No L2 cache
    • Variants
      • 266 MHz Introduced April 15, 1998
      • 300 MHz Introduced June 9, 1998
  • Mendocino – 0.25 µm process technology
    • Introduced August 24, 1998
    • 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
    • Number of transistors 19 million
    • 66 MHz system bus clock rate
    • Slot 1, Socket 370
    • 32 KB L1 cache
    • 128 KB integrated cache
    • Family 6 model 6
    • Variants
      • 300, 333 MHz Introduced August 24, 1998
      • 366, 400 MHz Introduced January 4, 1999
      • 433 MHz Introduced March 22, 1999
      • 466 MHz
      • 500 MHz Introduced August 2, 1999
      • 533 MHz Introduced January 4, 2000
      • 266 MHz (Mobile)
      • 300 MHz (Mobile)
      • 333 MHz (Mobile) Introduced April 5, 1999
      • 366 MHz (Mobile)
      • 400 MHz (Mobile)
      • 433 MHz (Mobile)
      • 450 MHz (Mobile) Introduced February 14, 2000
      • 466 MHz (Mobile)
      • 500 MHz (Mobile) Introduced February 14, 2000

Pentium II Xeon (chronological entry)
  • Introduced June 29, 1998
  • See main entry

Pentium III

  • Katmai – 0.25 µm process technology
    • Introduced February 26, 1999
    • Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
    • Number of transistors 9.5 million
    • 512 KB ½ bandwidth L2 External cache
    • 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
    • System Bus clock rate 100 MHz, 133 MHz (B-models)
    • Slot 1
    • Family 6 model 7
    • Variants
      • 450, 500 MHz Introduced February 26, 1999
      • 550 MHz Introduced May 17, 1999
      • 600 MHz Introduced August 2, 1999
      • 533, 600 MHz Introduced (133 MHz bus clock rate) September 27, 1999
  • Coppermine – 0.18 µm process technology
    • Introduced October 25, 1999
    • Number of transistors 28.1 million
    • 256 KB Advanced Transfer L2 Cache (Integrated)
    • 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
    • System Bus clock rate 100 MHz (E-models), 133 MHz (EB models)
    • Slot 1, Socket 370
    • Family 6 model 8
    • Variants
      • 500 MHz (100 MHz bus clock rate)
      • 533 MHz
      • 550 MHz (100 MHz bus clock rate)
      • 600 MHz
      • 600 MHz (100 MHz bus clock rate)
      • 650 MHz (100 MHz bus clock rate) Introduced October 25, 1999
      • 667 MHz Introduced October 25, 1999
      • 700 MHz (100 MHz bus clock rate) Introduced October 25, 1999
      • 733 MHz Introduced October 25, 1999
      • 750, 800 MHz (100 MHz bus clock rate) Introduced December 20, 1999
      • 850 MHz (100 MHz bus clock rate) Introduced March 20, 2000
      • 866 MHz Introduced March 20, 2000
      • 933 MHz Introduced May 24, 2000
      • 1000 MHz Introduced March 8, 2000 (not widely available at time of release)
      • 1100 MHz
      • 1133 MHz (first version recalled, later re-released)
      • 400, 450, 500 MHz (Mobile) Introduced October 25, 1999
      • 600, 650 MHz (Mobile) Introduced January 18, 2000
      • 700 MHz (Mobile) Introduced April 24, 2000
      • 750 MHz (Mobile) Introduced June 19, 2000
      • 800, 850 MHz (Mobile) Introduced September 25, 2000
      • 900, 1000 MHz (Mobile) Introduced March 19, 2001
  • Tualatin – 0.13 µm process technology
    • Introduced July 2001
    • Number of transistors 28.1 million
    • 32 KB L1 cache
    • 256 KB or 512 KB Advanced Transfer L2 cache (integrated)
    • 370-pin FC-PGA2 (flip-chip pin grid array) package
    • 133 MHz system bus clock rate
    • Socket 370
    • Family 6 model 11
    • Variants
      • 1133 MHz (256 KB L2)
      • 1133 MHz (512 KB L2)
      • 1200 MHz
      • 1266 MHz (512 KB L2)
      • 1333 MHz
      • 1400 MHz (512 KB L2)

Pentium II and III Xeon

  • PII Xeon
    • Variants
      • 400 MHz Introduced June 29, 1998
      • 450 MHz (512 KB L2 Cache) Introduced October 6, 1998
      • 450 MHz (1 MB and 2 MB L2 Cache) Introduced January 5, 1999
  • PIII Xeon
    • Introduced October 25, 1999
    • Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm
    • L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
    • Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
    • System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1–2 MB L2 cache)
    • System Bus Width 64 bits
    • Addressable memory 64 GB
    • Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1–2 MB L2)
    • Family 6 model 10
    • Variants
      • 500 MHz (0.25 µm process) Introduced March 17, 1999
      • 550 MHz (0.25 µm process) Introduced August 23, 1999
      • 600 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
      • 667 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
      • 733 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
      • 800 MHz (0.18 µm process, 256 KB L2 cache) Introduced January 12, 2000
      • 866 MHz (0.18 µm process, 256 KB L2 cache) Introduced April 10, 2000
      • 933 MHz (0.18 µm process, 256 KB L2 cache)
      • 1000 MHz (0.18 µm process, 256 KB L2 cache) Introduced August 22, 2000
      • 700 MHz (0.18 µm process, 1–2 MB L2 cache) Introduced May 22, 2000

Celeron (Pentium III Coppermine-based)

  • Coppermine-128, 0.18 µm process technology
    • Introduced March, 2000
    • Streaming SIMD Extensions (SSE)
    • Socket 370, FC-PGA processor package
    • Number of transistors: 28.1 million
    • 66 MHz system bus clock rate, 100 MHz system bus clock rate from January 3, 2001
    • 32 kB L1 cache
    • 128 kB Advanced Transfer L2 cache
    • Family 6 model 8
    • Variants
      • 533 MHz
      • 566 MHz
      • 600 MHz
      • 633, 667, 700 MHz Introduced June 26, 2000
      • 733, 766 MHz Introduced November 13, 2000
      • 800 MHz Introduced January 3, 2001
      • 850 MHz Introduced April 9, 2001
      • 900 MHz Introduced July 2, 2001
      • 950, 1000, 1100 MHz Introduced August 31, 2001
      • 550 MHz (Mobile)
      • 600, 650 MHz (Mobile) Introduced June 19, 2000
      • 700 MHz (Mobile) Introduced September 25, 2000
      • 750 MHz (Mobile) Introduced March 19, 2001
      • 800 MHz (Mobile)
      • 850 MHz (Mobile) Introduced July 2, 2001
      • 600 MHz (LV Mobile)
      • 500 MHz (ULV Mobile) Introduced January 30, 2001
      • 600 MHz (ULV Mobile)

XScale (chronological entry)
  • Introduced August 23, 2000
  • See main entry

Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)
  • Introduced April 2000 – July 2002
  • See main entries

Celeron (Pentium III Tualatin-based)

  • Tualatin Celeron – 0.13 µm process technology
    • 32 KB L1 cache
    • 256 KB Advanced Transfer L2 cache
    • 100 MHz system bus clock rate
    • Socket 370
    • Family 6 model 11
    • Variants
      • 1.0 GHz
      • 1.1 GHz
      • 1.2 GHz
      • 1.3 GHz
      • 1.4 GHz

Pentium M

  • Banias 0.13 µm process technology
    • Introduced March 2003
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
    • Number of transistors 77 million
    • Micro-FCPGA, Micro-FCBGA processor package
    • Heart of the Intel mobile Centrino system
    • 400 MHz Netburst-style system bus
    • Family 6 model 9
    • Variants
      • 900 MHz (ultra low voltage)
      • 1.0 GHz (ultra low voltage)
      • 1.1 GHz (low voltage)
      • 1.2 GHz (low voltage)
      • 1.3 GHz
      • 1.4 GHz
      • 1.5 GHz
      • 1.6 GHz
      • 1.7 GHz
  • Dothan 0.09 µm (90 nm) process technology
    • Introduced May 2004
    • 2 MB L2 cache
    • 140 million transistors
    • Revised data prefetch unit
    • 400 MHz Netburst-style system bus
    • 21W TDP
    • Family 6 model 13
    • Variants
      • 1.00 GHz (Pentium M 723) (ultra low voltage, 5W TDP)
      • 1.10 GHz (Pentium M 733) (ultra low voltage, 5W TDP)
      • 1.20 GHz (Pentium M 753) (ultra low voltage, 5W TDP)
      • 1.30 GHz (Pentium M 718) (low voltage, 10W TDP)
      • 1.40 GHz (Pentium M 738) (low voltage, 10W TDP)
      • 1.50 GHz (Pentium M 758) (low voltage, 10W TDP)
      • 1.60 GHz (Pentium M 778) (low voltage, 10W TDP)
      • 1.40 GHz (Pentium M 710)
      • 1.50 GHz (Pentium M 715)
      • 1.60 GHz (Pentium M 725)
      • 1.70 GHz (Pentium M 735)
      • 1.80 GHz (Pentium M 745)
      • 2.00 GHz (Pentium M 755)
      • 2.10 GHz (Pentium M 765)
  • Dothan 533 0.09 µm (90 nm) process technology
    • Introduced Q1 2005
    • Same as Dothan except with a 533 MHz NetBurst-style system bus and 27W TDP
    • Variants
      • 1.60 GHz (Pentium M 730)
      • 1.73 GHz (Pentium M 740)
      • 1.86 GHz (Pentium M 750)
      • 2.00 GHz (Pentium M 760)
      • 2.13 GHz (Pentium M 770)
      • 2.26 GHz (Pentium M 780)
  • Stealey 0.09 µm (90 nm) process technology
    • Introduced Q2 2007
    • 512 KB L2, 3W TDP
    • Variants
      • 600 MHz (A100)
      • 800 MHz (A110)

Celeron M

  • Banias-512 0.13 µm process technology
    • Introduced March 2003
    • 64 KB L1 cache
    • 512 KB L2 cache (integrated)
    • SSE2 SIMD instructions
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Family 6 model 9
    • Variants
      • 310 – 1.20 GHz
      • 320 – 1.30 GHz
      • 330 – 1.40 GHz
      • 340 – 1.50 GHz
  • Dothan-1024 90 nm process technology
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • SSE2 SIMD instructions
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Variants
      • 350 – 1.30 GHz
      • 350J – 1.30 GHz, with Execute Disable bit
      • 360 – 1.40 GHz
      • 360J – 1.40 GHz, with Execute Disable bit
      • 370 – 1.50 GHz, with Execute Disable bit
        • Family 6, Model 13, Stepping 8
      • 380 – 1.60 GHz, with Execute Disable bit
      • 390 – 1.70 GHz, with Execute Disable bit
  • Yonah-1024 65 nm process technology
    • 64 KB L1 cache
    • 1 MB L2 cache (integrated)
    • SSE3 SIMD instructions, 533 MHz front-side bus, execute-disable bit
    • No SpeedStep technology, is not part of the 'Centrino' package
    • Variants
      • 410 – 1.46 GHz
      • 420 – 1.60 GHz,
      • 423 – 1.06 GHz (ultra low voltage)
      • 430 – 1.73 GHz
      • 440 – 1.86 GHz
      • 443 – 1.20 GHz (ultra low voltage)
      • 450 – 2.00 GHz

Intel Core

  • Yonah 0.065 µm (65 nm) process technology
    • Introduced January 2006
    • 533/667 MHz front side bus
    • 2 MB (Shared on Duo) L2 cache
    • SSE3 SIMD instructions
    • 31W TDP (T versions)
    • Family 6, Model 14
    • Variants:
      • Intel Core Duo T2700 2.33 GHz
      • Intel Core Duo T2600 2.16 GHz
      • Intel Core Duo T2500 2 GHz
      • Intel Core Duo T2450 2 GHz
      • Intel Core Duo T2400 1.83 GHz
      • Intel Core Duo T2300 1.66 GHz
      • Intel Core Duo T2050 1.6 GHz
      • Intel Core Duo T2300e 1.66 GHz
      • Intel Core Duo T2080 1.73 GHz
      • Intel Core Duo L2500 1.83 GHz (low voltage, 15W TDP)
      • Intel Core Duo L2400 1.66 GHz (low voltage, 15W TDP)
      • Intel Core Duo L2300 1.5 GHz (low voltage, 15W TDP)
      • Intel Core Duo U2500 1.2 GHz (ultra low voltage, 9W TDP)
      • Intel Core Solo T1350 1.86 GHz (533 FSB)
      • Intel Core Solo T1300 1.66 GHz
      • Intel Core Solo T1200 1.5 GHz 

Dual-Core Xeon LV

  • Sossaman 0.065 µm (65 nm) process technology
    • Introduced March 2006
    • Based on Yonah core, with SSE3 SIMD instructions
    • 667 MHz frontside bus
    • 2 MB Shared L2 cache
    • Variants
      • 2.0 GHz

32-bit processor:Net Burst Microarchitecture


Pentium 4

  • 0.18 µm process technology (1.40 and 1.50 GHz)
    • Introduced November 20, 2000
    • L2 cache was 256 KB Advanced Transfer Cache (Integrated)
    • Processor Package Style was PGA423, PGA478
    • System Bus clock rate 400 MHz
    • SSE2 SIMD Extensions
    • Number of Transistors 42 million
    • Used in desktops and entry-level workstations
  • 0.18 µm process technology (1.7 GHz)
    • Introduced April 23, 2001
    • See the 1.4 and 1.5 chips for details
  • 0.18 µm process technology (1.6 and 1.8 GHz)
    • Introduced July 2, 2001
    • See 1.4 and 1.5 chips for details
    • Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
    • Power <1 watt in Battery Optimized Mode
    • Used in full-size and then light mobile PCs
  • 0.18 µm process technology Willamette (1.9 and 2.0 GHz)
    • Introduced August 27, 2001
    • See 1.4 and 1.5 chips for details
  • Family 15 model 1
  • Pentium 4 (2 GHz, 2.20 GHz)
    • Introduced January 7, 2002
  • Pentium 4 (2.4 GHz)
    • Introduced April 2, 2002
  • 0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6, 2.8(OEM),3.0(OEM) GHz)
    • Improved branch prediction and other microcodes tweaks
    • 512 KB integrated L2 cache
    • Number of transistors 55 million
    • 400 MHz system bus.
  • Family 15 model 2
  • 0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
    • 533 MHz system bus. (3.06 includes Intel's Hyper-Threading technology).
  • 0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
    • 800 MHz system bus (all versions include Hyper-Threading)
    • 6500 to 10000 MIPS

Itanium (chronological entry)
  • Introduced 2001
  • See main entry

Xeon

  • Official designation now Xeon, i.e. not "Pentium 4 Xeon"
  • Xeon 1.4, 1.5, 1.7 GHz
    • Introduced May 21, 2001
    • L2 cache was 256 KB Advanced Transfer Cache (Integrated)
    • Processor Package Style was Organic Land Grid Array 603 (OLGA 603)
    • System Bus clock rate 400 MHz
    • SSE2 SIMD Extensions
    • Used in high-performance and mid-range dual processor enabled workstations
  • Xeon 2.0 GHz and up to 3.6 GHz
    • Introduced September 25, 2001

Itanium 2 (chronological entry)
  • Introduced July 2002
  • See main entry

Mobile Pentium 4-M[edit]

  • 0.13 µm process technology
  • 55 million transistors
  • cache L2 512 KB
  • BUS a 400 MHz
  • Supports up to 1 GB of DDR 266 MHz Memory
  • Supports ACPI 2.0 and APM 1.2 System Power Management
  • 1.3 V – 1.2 V (SpeedStep)
  • Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
  • Sleep Power 5 W (1.2 V)
  • Deeper Sleep Power = 2.9 W (1.0 V)
    • 1.40 GHz – 23 April 2002
    • 1.50 GHz – 23 April 2002
    • 1.60 GHz – 4 March 2002
    • 1.70 GHz – 4 March 2002
    • 1.80 GHz – 23 April 2002
    • 1.90 GHz – 24 June 2002
    • 2.00 GHz – 24 June 2002
    • 2.20 GHz – 16 September 2002
    • 2.40 GHz – 14 January 2003
    • 2.50 GHz – 16 April 2003
    • 2.60 GHz – 11 June 2003

Pentium 4 EE

  • Introduced September 2003
  • EE = "Extreme Edition"
  • Built from the Xeon's "Gallatin" core, but with 2 MB cache

Pentium 4E

  • Introduced February 2004
  • built on 0.09 µm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MB L2 cache
  • 533 MHz system bus (2.4A and 2.8A only)
  • Number of Transistors 125 million on 1 MB Models
  • Number of Transistors 169 million on 2 MB Models
  • 800 MHz system bus (all other models)
  • Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
  • The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater bandwidth.
  • 7500 to 11000 MIPS
  • LGA 775 versions are in the 5xx series (32-bit) and 5x1 series (with Intel 64)
  • The 6xx series has 2 MB L2 cache and Intel 64

Pentium 4F

  • Introduced Spring 2004
  • same core as 4E, "Prescott"
  • 3.2–3.6 GHz
  • starting with the D0 stepping of this processor, Intel 64 64-bit extensions has also been incorporated

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